The present invention relates to a DC-DC converter for converting a DC input voltage into a target output voltage by repeatedly storing energy in an inductor and releasing the energy from the inductor through the ON/OFF operation of a switching device, and to a control circuit thereof.
In a power supply circuit in which an input DC voltage is input from an input DC power supply, and output DC voltages serving as power supply voltages for various electronic circuits are output, for example, when an output DC voltage higher than the input DC voltage is output, a step-up converter is used.
As a general step-up converter and its control circuit, a converter and its control circuit configured as shown in FIG. 9 are known. A first conventional step-up converter and its control circuit will be described below referring to FIG. 9. In FIG. 9, numeral 1 designates an input DC power supply, such as a battery, numeral 2 designates an inductor, numeral 3 designates a switching device formed of a MOSFET, numeral 4 designates a rectifying means formed of a diode, numeral 5 designates a smoothing means formed of a capacitor, and numeral 30 designates a control circuit. The inductor 2 and the switching device 3 are connected in series, and this series circuit is connected in parallel with the input DC power supply 1. The rectifying means 4 is connected to the connection point of the inductor 2 and the switching device 3, and the output of the rectifying means 4 is smoothed using the smoothing means 5, and an output DC voltage Vo is output. The inductor 2, the switching device 3, the rectifying means 4 and the smoothing means 5 described above constitute a step-up converter. The control circuit 30 detects the output DC voltage, supplies a drive signal DR to the switching device 3, and controls the ON/OFF operation of the switching device 3.
The control circuit 30 comprises an error-amplifier circuit 31, an oscillating circuit 32 and a comparator 33. The error-amplifier circuit 31 detects the output DC voltage Vo, and generates an error signal Ve that is obtained by amplifying the error between the output DC voltage Vo and a target value. The error signal Ve lowers when the output DC voltage Vo is higher than the target value, and rises when the output DC voltage Vo is lower than the target value. The oscillating circuit 32 generates a triangular wave signal Vt that varies according to a predetermined cycle. The amplitude of the oscillation of the triangular wave signal Vt is assumed to be Et. The comparator 33 compares the triangular wave signal Vt with the error signal Ve, and generates a drive signal DR that becomes high when the error signal Ve is larger.
FIG. 10 is a waveform diagram showing the operations of the various sections of the control circuit 30, showing the triangular wave signal Vt, the error signal Ve, and the drive signal DR. The pulse width of the drive signal DR, that is, the ON time of the switching device 3, becomes larger as the error signal Ve rises.
In FIG. 9, when the switching device 3 is ON, an input DC voltage Vi is applied to the inductor 2, a current flows from the input DC power supply 1 to the switching device 3 via the inductor 2, and energy is stored in the inductor 2. Then, when the switching device 3 is OFF, the voltage difference (Vi−Vo) between the output DC voltage Vo and the input DC voltage Vi is applied to the inductor 2, a current flows from the input DC power supply 1 to the rectifying means 4 via the inductor 2, and the energy stored in the inductor 2 is released. When it is assumed that the ratio (referred to as “duty ratio”) of the ON time (the pulse width of the drive signal DR) in one switching cycle (the cycle of the triangular wave signal Vt) of the switching device 3 is D, the output DC voltage Vo is represented by Vo=Vi/(1−D). The duty ratio D becomes higher as the error signal Ve rises. In other words, the duty ratio D is adjusted using the control circuit 30 so that the output DC voltage Vo reaches the target value.
The control circuit disclosed in Japanese Patent Application Laid-open No. Hei 5-76169 is known as an example of a control circuit being improved in versatility by using a clock signal instead of the triangular wave signal Vt of the control circuit 30 of the conventional step-up converter described above.
As a second conventional example, the step-up converter and its control circuit disclosed in Japanese Patent Application Laid-open No. Hei 5-76169 are described below referring to FIG. 11. In FIG. 11, the configuration of the step-up converter comprising an input DC power supply 1, an inductor 2, a switching device 3, a rectifying means 4 and a smoothing means 5 is similar to that shown in FIG. 9. Numeral 40 designates a control circuit that detects the output DC voltage of the converter, supplies a drive signal DR to the switching device 3, and controls the ON/OFF operation of the switching device 3.
The control circuit 40 comprises an error-amplifier circuit 41, an oscillating circuit 42, a constant-current source circuit 43, a capacitor 44, a comparator 45, a latch circuit 46 and a transistor 47. The error-amplifier circuit 41 detects the output DC voltage Vo, and generates an error signal Ve that is obtained by amplifying the error between the output DC voltage Vo and a target value. The error signal Ve lowers when the output DC voltage Vo is higher than the target value, and rises when the output DC voltage Vo is lower than the target value. The oscillating circuit 42 generates a clock signal Vck having a predetermined cycle and sets the latch circuit 46. The constant-current source circuit 43 outputs a constant current Io and charges the capacitor 44. The electrostatic capacitance of the capacitor 44 is assumed to be C4. The comparator 45 compares the error signal Ve with the charged voltage V4 of the capacitor 44. When the charged voltage V4 of the capacitor 44 is higher than the error signal Ve, the comparator 44 outputs a high level signal, and resets the latch circuit 46. The output Q of the latch circuit 46 becomes high when the latch circuit 46 is set, and becomes low when the latch circuit 46 is reset, whereby the latch circuit 46 generates the drive signal DR. The drive signal DR is input to the gate of the switching device 3, turning ON the switching device 3 when the drive signal DR is high, and turning OFF the switching device 3 when the drive signal DR is low. On the other hand, the inverted output QB of the latch circuit 46 drives the transistor 47 so that the capacitor 44 is short-circuited and discharged while the drive signal DR is low, that is, while the switching device 3 is OFF.
FIG. 12 is a waveform diagram showing the operations of the various sections of the control circuit 40, showing the clock signal Vck, the error signal Ve, the charged voltage V4 of the capacitor 44, the reset signal R supplied to the latch circuit 46, and the drive signal DR. The pulse width of the drive signal DR, that is, the ON time of the switching device 3, becomes larger as the error signal Ve rises.
In the step-up converters according to the conventional examples configured as described above, the relationship between the error signal Ve and the duty ratio D is linear. However, the relationship between the duty ratio D and the output DC voltage Vo is represented by Vo=Vi/(1−D) and nonlinear.
For example, in the case of the first conventional step-up converter and its control circuit 30 shown in FIG. 9, when it is assumed that the triangular wave signal Vt changes between 0 and Et for the sake of simplicity, the duty ratio D is represented by D=Ve/Et using the error signal Ve. The output DC voltage Vo is thus represented by Expression (1) described below.Vo=Vi/(1−D)=Vi·Et/(Et−Ve)  (1)
In other words, the tendency (∂Vo/∂Ve) of increasing the output DC voltage Vo becomes larger as the error signal Ve rises.
On the other hand, in the case of the second conventional step-up converter and its control circuit 40, the ON time Ton of the switching device 3 is represented by Ton=Ve·C4 Io using the error signal Ve, the electrostatic capacitance C4 of the capacitor 44 and the constant current Io. When it is assumed that the cycle of the clock signal Vck, that is, the switching cycle, is Ts, the output DC voltage Vo is represented by Expression (2) described below because the duty ratio D=Ton/Ts.
                                                        Vo              =                              Vi                ·                                  Ts                  /                                      (                                          Ts                      -                      Ton                                        )                                                                                                                          =                              Vi                ·                                  Ts                  /                                      (                                          Ts                      -                                                                        Ve                          ·                          C                                                ⁢                                                                                                  ⁢                                                  4                          /                          Io                                                                                      )                                                                                                          (        2        )            
Hence, (∂Vo/∂Ve) becomes larger as the error signal Ve rises, just as in the case of the first conventional example. This indicates that, as the output DC voltage Vo is higher than the input DC voltage Vi, the output DC voltage Vo fluctuates significantly when the error signal Ve changes slightly, causing a problem of making the output DC voltage Vo easy to become unstable.